Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. Copyright 2022-2023 Advanced Micro Devices, Inc. All Rights Reserved.
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2023.1 (win64) Build 3865809 Sun May  7 15:05:29 MDT 2023
| Date         : Thu Jun  8 10:54:21 2023
| Host         : DESKTOP-5QEHRRG running 64-bit major release  (build 9200)
| Command      : report_timing_summary -max_paths 10 -report_unconstrained -file basys3top_timing_summary_routed.rpt -pb basys3top_timing_summary_routed.pb -rpx basys3top_timing_summary_routed.rpx -warn_on_violation
| Design       : basys3top
| Device       : 7a35t-cpg236
| Speed File   : -1  PRODUCTION 1.23 2018-06-13
| Design State : Routed
------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------

Timing Summary Report

------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------

  Enable Multi Corner Analysis               :  Yes
  Enable Pessimism Removal                   :  Yes
  Pessimism Removal Resolution               :  Nearest Common Node
  Enable Input Delay Default Clock           :  No
  Enable Preset / Clear Arcs                 :  No
  Disable Flight Delays                      :  No
  Ignore I/O Paths                           :  No
  Timing Early Launch at Borrowing Latches   :  No
  Borrow Time for Max Delay Exceptions       :  Yes
  Merge Timing Exceptions                    :  Yes

  Corner  Analyze    Analyze    
  Name    Max Paths  Min Paths  
  ------  ---------  ---------  
  Slow    Yes        Yes        
  Fast    Yes        Yes        


------------------------------------------------------------------------------------------------
| Report Methodology
| ------------------
------------------------------------------------------------------------------------------------

Rule       Severity  Description                    Violations  
---------  --------  -----------------------------  ----------  
TIMING-18  Warning   Missing input or output delay  12          

Note: This report is based on the most recent report_methodology run and may not be up-to-date. Run report_methodology on the current design for the latest report.



check_timing report

Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (0)
5. checking no_input_delay (0)
6. checking no_output_delay (9)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)

1. checking no_clock (0)
------------------------
 There are 0 register/latch pins with no clock.


2. checking constant_clock (0)
------------------------------
 There are 0 register/latch pins with constant_clock.


3. checking pulse_width_clock (0)
---------------------------------
 There are 0 register/latch pins which need pulse_width check


4. checking unconstrained_internal_endpoints (0)
------------------------------------------------
 There are 0 pins that are not constrained for maximum delay.

 There are 0 pins that are not constrained for maximum delay due to constant clock.


5. checking no_input_delay (0)
------------------------------
 There are 0 input ports with no input delay specified.

 There are 0 input ports with no input delay but user has a false path constraint.


6. checking no_output_delay (9)
-------------------------------
 There are 9 ports with no output delay specified. (HIGH)

 There are 0 ports with no output delay but user has a false path constraint

 There are 0 ports with no output delay but with a timing clock defined on it or propagating through it


7. checking multiple_clock (0)
------------------------------
 There are 0 register/latch pins with multiple clocks.


8. checking generated_clocks (0)
--------------------------------
 There are 0 generated clocks that are not connected to a clock source.


9. checking loops (0)
---------------------
 There are 0 combinational loops in the design.


10. checking partial_input_delay (0)
------------------------------------
 There are 0 input ports with partial input delay specified.


11. checking partial_output_delay (0)
-------------------------------------
 There are 0 ports with partial output delay specified.


12. checking latch_loops (0)
----------------------------
 There are 0 combinational latch loops in the design through latch input



------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------

    WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
    -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
      7.808        0.000                      0                   13        0.252        0.000                      0                   13        4.500        0.000                       0                    14  


All user specified timing constraints are met.


------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------

Clock  Waveform(ns)       Period(ns)      Frequency(MHz)
-----  ------------       ----------      --------------
clk    {0.000 5.000}      10.000          100.000         


------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------

Clock             WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints     WPWS(ns)     TPWS(ns)  TPWS Failing Endpoints  TPWS Total Endpoints  
-----             -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------     --------     --------  ----------------------  --------------------  
clk                 7.808        0.000                      0                   13        0.252        0.000                      0                   13        4.500        0.000                       0                    14  


------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------

From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock          WNS(ns)      TNS(ns)  TNS Failing Endpoints  TNS Total Endpoints      WHS(ns)      THS(ns)  THS Failing Endpoints  THS Total Endpoints  
----------    ----------    --------          -------      -------  ---------------------  -------------------      -------      -------  ---------------------  -------------------  


------------------------------------------------------------------------------------------------
| User Ignored Path Table
| -----------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock    
----------    ----------    --------    


------------------------------------------------------------------------------------------------
| Unconstrained Path Table
| ------------------------
------------------------------------------------------------------------------------------------

Path Group    From Clock    To Clock    
----------    ----------    --------    
(none)        clk                         


------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------


---------------------------------------------------------------------------------------------------
From Clock:  clk
  To Clock:  clk

Setup :            0  Failing Endpoints,  Worst Slack        7.808ns,  Total Violation        0.000ns
Hold  :            0  Failing Endpoints,  Worst Slack        0.252ns,  Total Violation        0.000ns
PW    :            0  Failing Endpoints,  Worst Slack        4.500ns,  Total Violation        0.000ns
---------------------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             7.808ns  (required time - arrival time)
  Source:                 sseg/count_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk rise@10.000ns - clk rise@0.000ns)
  Data Path Delay:        2.199ns  (logic 1.581ns (71.889%)  route 0.618ns (28.111%))
  Logic Levels:           4  (CARRY4=4)
  Clock Path Skew:        -0.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
    Source Clock Delay      (SCD):    5.142ns
    Clock Pessimism Removal (CPR):    0.274ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.621     5.142    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.456     5.598 r  sseg/count_reg[1]/Q
                         net (fo=1, routed)           0.618     6.216    sseg/count_reg_n_0_[1]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.674     6.890 r  sseg/count_reg[0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     6.890    sseg/count_reg[0]_i_1_n_0
    SLICE_X65Y28         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.004 r  sseg/count_reg[4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     7.004    sseg/count_reg[4]_i_1_n_0
    SLICE_X65Y29         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.118 r  sseg/count_reg[8]_i_1/CO[3]
                         net (fo=1, routed)           0.000     7.118    sseg/count_reg[8]_i_1_n_0
    SLICE_X65Y30         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.223     7.341 r  sseg/count_reg[12]_i_1/O[0]
                         net (fo=1, routed)           0.000     7.341    sseg/count_reg[12]_i_1_n_7
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)       10.000    10.000 r  
    W5                                                0.000    10.000 r  clk (IN)
                         net (fo=0)                   0.000    10.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.508    14.849    sseg/clk
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/C
                         clock pessimism              0.274    15.123    
                         clock uncertainty           -0.035    15.088    
    SLICE_X65Y30         FDRE (Setup_fdre_C_D)        0.062    15.150    sseg/count_reg[12]
  -------------------------------------------------------------------
                         required time                         15.150    
                         arrival time                          -7.341    
  -------------------------------------------------------------------
                         slack                                  7.808    

Slack (MET) :             7.811ns  (required time - arrival time)
  Source:                 sseg/count_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[9]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk rise@10.000ns - clk rise@0.000ns)
  Data Path Delay:        2.196ns  (logic 1.578ns (71.851%)  route 0.618ns (28.149%))
  Logic Levels:           3  (CARRY4=3)
  Clock Path Skew:        -0.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
    Source Clock Delay      (SCD):    5.142ns
    Clock Pessimism Removal (CPR):    0.274ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.621     5.142    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.456     5.598 r  sseg/count_reg[1]/Q
                         net (fo=1, routed)           0.618     6.216    sseg/count_reg_n_0_[1]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.674     6.890 r  sseg/count_reg[0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     6.890    sseg/count_reg[0]_i_1_n_0
    SLICE_X65Y28         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.004 r  sseg/count_reg[4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     7.004    sseg/count_reg[4]_i_1_n_0
    SLICE_X65Y29         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     7.338 r  sseg/count_reg[8]_i_1/O[1]
                         net (fo=1, routed)           0.000     7.338    sseg/count_reg[8]_i_1_n_6
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[9]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)       10.000    10.000 r  
    W5                                                0.000    10.000 r  clk (IN)
                         net (fo=0)                   0.000    10.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.508    14.849    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[9]/C
                         clock pessimism              0.274    15.123    
                         clock uncertainty           -0.035    15.088    
    SLICE_X65Y29         FDRE (Setup_fdre_C_D)        0.062    15.150    sseg/count_reg[9]
  -------------------------------------------------------------------
                         required time                         15.150    
                         arrival time                          -7.338    
  -------------------------------------------------------------------
                         slack                                  7.811    

Slack (MET) :             7.832ns  (required time - arrival time)
  Source:                 sseg/count_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk rise@10.000ns - clk rise@0.000ns)
  Data Path Delay:        2.175ns  (logic 1.557ns (71.579%)  route 0.618ns (28.421%))
  Logic Levels:           3  (CARRY4=3)
  Clock Path Skew:        -0.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
    Source Clock Delay      (SCD):    5.142ns
    Clock Pessimism Removal (CPR):    0.274ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.621     5.142    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.456     5.598 r  sseg/count_reg[1]/Q
                         net (fo=1, routed)           0.618     6.216    sseg/count_reg_n_0_[1]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.674     6.890 r  sseg/count_reg[0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     6.890    sseg/count_reg[0]_i_1_n_0
    SLICE_X65Y28         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.004 r  sseg/count_reg[4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     7.004    sseg/count_reg[4]_i_1_n_0
    SLICE_X65Y29         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313     7.317 r  sseg/count_reg[8]_i_1/O[3]
                         net (fo=1, routed)           0.000     7.317    sseg/count_reg[8]_i_1_n_4
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)       10.000    10.000 r  
    W5                                                0.000    10.000 r  clk (IN)
                         net (fo=0)                   0.000    10.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.508    14.849    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[11]/C
                         clock pessimism              0.274    15.123    
                         clock uncertainty           -0.035    15.088    
    SLICE_X65Y29         FDRE (Setup_fdre_C_D)        0.062    15.150    sseg/count_reg[11]
  -------------------------------------------------------------------
                         required time                         15.150    
                         arrival time                          -7.317    
  -------------------------------------------------------------------
                         slack                                  7.832    

Slack (MET) :             7.906ns  (required time - arrival time)
  Source:                 sseg/count_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk rise@10.000ns - clk rise@0.000ns)
  Data Path Delay:        2.101ns  (logic 1.483ns (70.578%)  route 0.618ns (29.422%))
  Logic Levels:           3  (CARRY4=3)
  Clock Path Skew:        -0.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
    Source Clock Delay      (SCD):    5.142ns
    Clock Pessimism Removal (CPR):    0.274ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.621     5.142    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.456     5.598 r  sseg/count_reg[1]/Q
                         net (fo=1, routed)           0.618     6.216    sseg/count_reg_n_0_[1]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.674     6.890 r  sseg/count_reg[0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     6.890    sseg/count_reg[0]_i_1_n_0
    SLICE_X65Y28         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.004 r  sseg/count_reg[4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     7.004    sseg/count_reg[4]_i_1_n_0
    SLICE_X65Y29         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     7.243 r  sseg/count_reg[8]_i_1/O[2]
                         net (fo=1, routed)           0.000     7.243    sseg/count_reg[8]_i_1_n_5
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)       10.000    10.000 r  
    W5                                                0.000    10.000 r  clk (IN)
                         net (fo=0)                   0.000    10.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.508    14.849    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/C
                         clock pessimism              0.274    15.123    
                         clock uncertainty           -0.035    15.088    
    SLICE_X65Y29         FDRE (Setup_fdre_C_D)        0.062    15.150    sseg/count_reg[10]
  -------------------------------------------------------------------
                         required time                         15.150    
                         arrival time                          -7.243    
  -------------------------------------------------------------------
                         slack                                  7.906    

Slack (MET) :             7.922ns  (required time - arrival time)
  Source:                 sseg/count_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk rise@10.000ns - clk rise@0.000ns)
  Data Path Delay:        2.085ns  (logic 1.467ns (70.352%)  route 0.618ns (29.648%))
  Logic Levels:           3  (CARRY4=3)
  Clock Path Skew:        -0.019ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.849ns = ( 14.849 - 10.000 ) 
    Source Clock Delay      (SCD):    5.142ns
    Clock Pessimism Removal (CPR):    0.274ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.621     5.142    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.456     5.598 r  sseg/count_reg[1]/Q
                         net (fo=1, routed)           0.618     6.216    sseg/count_reg_n_0_[1]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.674     6.890 r  sseg/count_reg[0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     6.890    sseg/count_reg[0]_i_1_n_0
    SLICE_X65Y28         CARRY4 (Prop_carry4_CI_CO[3])
                                                      0.114     7.004 r  sseg/count_reg[4]_i_1/CO[3]
                         net (fo=1, routed)           0.000     7.004    sseg/count_reg[4]_i_1_n_0
    SLICE_X65Y29         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.223     7.227 r  sseg/count_reg[8]_i_1/O[0]
                         net (fo=1, routed)           0.000     7.227    sseg/count_reg[8]_i_1_n_7
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)       10.000    10.000 r  
    W5                                                0.000    10.000 r  clk (IN)
                         net (fo=0)                   0.000    10.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.508    14.849    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[8]/C
                         clock pessimism              0.274    15.123    
                         clock uncertainty           -0.035    15.088    
    SLICE_X65Y29         FDRE (Setup_fdre_C_D)        0.062    15.150    sseg/count_reg[8]
  -------------------------------------------------------------------
                         required time                         15.150    
                         arrival time                          -7.227    
  -------------------------------------------------------------------
                         slack                                  7.922    

Slack (MET) :             7.924ns  (required time - arrival time)
  Source:                 sseg/count_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk rise@10.000ns - clk rise@0.000ns)
  Data Path Delay:        2.082ns  (logic 1.464ns (70.310%)  route 0.618ns (29.690%))
  Logic Levels:           2  (CARRY4=2)
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.848ns = ( 14.848 - 10.000 ) 
    Source Clock Delay      (SCD):    5.142ns
    Clock Pessimism Removal (CPR):    0.274ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.621     5.142    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.456     5.598 r  sseg/count_reg[1]/Q
                         net (fo=1, routed)           0.618     6.216    sseg/count_reg_n_0_[1]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.674     6.890 r  sseg/count_reg[0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     6.890    sseg/count_reg[0]_i_1_n_0
    SLICE_X65Y28         CARRY4 (Prop_carry4_CI_O[1])
                                                      0.334     7.224 r  sseg/count_reg[4]_i_1/O[1]
                         net (fo=1, routed)           0.000     7.224    sseg/count_reg[4]_i_1_n_6
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)       10.000    10.000 r  
    W5                                                0.000    10.000 r  clk (IN)
                         net (fo=0)                   0.000    10.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.507    14.848    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[5]/C
                         clock pessimism              0.274    15.122    
                         clock uncertainty           -0.035    15.087    
    SLICE_X65Y28         FDRE (Setup_fdre_C_D)        0.062    15.149    sseg/count_reg[5]
  -------------------------------------------------------------------
                         required time                         15.149    
                         arrival time                          -7.224    
  -------------------------------------------------------------------
                         slack                                  7.924    

Slack (MET) :             7.945ns  (required time - arrival time)
  Source:                 sseg/count_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk rise@10.000ns - clk rise@0.000ns)
  Data Path Delay:        2.061ns  (logic 1.443ns (70.007%)  route 0.618ns (29.993%))
  Logic Levels:           2  (CARRY4=2)
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.848ns = ( 14.848 - 10.000 ) 
    Source Clock Delay      (SCD):    5.142ns
    Clock Pessimism Removal (CPR):    0.274ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.621     5.142    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.456     5.598 r  sseg/count_reg[1]/Q
                         net (fo=1, routed)           0.618     6.216    sseg/count_reg_n_0_[1]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.674     6.890 r  sseg/count_reg[0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     6.890    sseg/count_reg[0]_i_1_n_0
    SLICE_X65Y28         CARRY4 (Prop_carry4_CI_O[3])
                                                      0.313     7.203 r  sseg/count_reg[4]_i_1/O[3]
                         net (fo=1, routed)           0.000     7.203    sseg/count_reg[4]_i_1_n_4
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)       10.000    10.000 r  
    W5                                                0.000    10.000 r  clk (IN)
                         net (fo=0)                   0.000    10.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.507    14.848    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[7]/C
                         clock pessimism              0.274    15.122    
                         clock uncertainty           -0.035    15.087    
    SLICE_X65Y28         FDRE (Setup_fdre_C_D)        0.062    15.149    sseg/count_reg[7]
  -------------------------------------------------------------------
                         required time                         15.149    
                         arrival time                          -7.203    
  -------------------------------------------------------------------
                         slack                                  7.945    

Slack (MET) :             8.019ns  (required time - arrival time)
  Source:                 sseg/count_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk rise@10.000ns - clk rise@0.000ns)
  Data Path Delay:        1.987ns  (logic 1.369ns (68.890%)  route 0.618ns (31.110%))
  Logic Levels:           2  (CARRY4=2)
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.848ns = ( 14.848 - 10.000 ) 
    Source Clock Delay      (SCD):    5.142ns
    Clock Pessimism Removal (CPR):    0.274ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.621     5.142    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.456     5.598 r  sseg/count_reg[1]/Q
                         net (fo=1, routed)           0.618     6.216    sseg/count_reg_n_0_[1]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.674     6.890 r  sseg/count_reg[0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     6.890    sseg/count_reg[0]_i_1_n_0
    SLICE_X65Y28         CARRY4 (Prop_carry4_CI_O[2])
                                                      0.239     7.129 r  sseg/count_reg[4]_i_1/O[2]
                         net (fo=1, routed)           0.000     7.129    sseg/count_reg[4]_i_1_n_5
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)       10.000    10.000 r  
    W5                                                0.000    10.000 r  clk (IN)
                         net (fo=0)                   0.000    10.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.507    14.848    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[6]/C
                         clock pessimism              0.274    15.122    
                         clock uncertainty           -0.035    15.087    
    SLICE_X65Y28         FDRE (Setup_fdre_C_D)        0.062    15.149    sseg/count_reg[6]
  -------------------------------------------------------------------
                         required time                         15.149    
                         arrival time                          -7.129    
  -------------------------------------------------------------------
                         slack                                  8.019    

Slack (MET) :             8.035ns  (required time - arrival time)
  Source:                 sseg/count_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk rise@10.000ns - clk rise@0.000ns)
  Data Path Delay:        1.971ns  (logic 1.353ns (68.638%)  route 0.618ns (31.362%))
  Logic Levels:           2  (CARRY4=2)
  Clock Path Skew:        -0.020ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.848ns = ( 14.848 - 10.000 ) 
    Source Clock Delay      (SCD):    5.142ns
    Clock Pessimism Removal (CPR):    0.274ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.621     5.142    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.456     5.598 r  sseg/count_reg[1]/Q
                         net (fo=1, routed)           0.618     6.216    sseg/count_reg_n_0_[1]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[1]_CO[3])
                                                      0.674     6.890 r  sseg/count_reg[0]_i_1/CO[3]
                         net (fo=1, routed)           0.000     6.890    sseg/count_reg[0]_i_1_n_0
    SLICE_X65Y28         CARRY4 (Prop_carry4_CI_O[0])
                                                      0.223     7.113 r  sseg/count_reg[4]_i_1/O[0]
                         net (fo=1, routed)           0.000     7.113    sseg/count_reg[4]_i_1_n_7
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)       10.000    10.000 r  
    W5                                                0.000    10.000 r  clk (IN)
                         net (fo=0)                   0.000    10.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.507    14.848    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[4]/C
                         clock pessimism              0.274    15.122    
                         clock uncertainty           -0.035    15.087    
    SLICE_X65Y28         FDRE (Setup_fdre_C_D)        0.062    15.149    sseg/count_reg[4]
  -------------------------------------------------------------------
                         required time                         15.149    
                         arrival time                          -7.113    
  -------------------------------------------------------------------
                         slack                                  8.035    

Slack (MET) :             8.188ns  (required time - arrival time)
  Source:                 sseg/count_reg[1]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Setup (Max at Slow Process Corner)
  Requirement:            10.000ns  (clk rise@10.000ns - clk rise@0.000ns)
  Data Path Delay:        1.838ns  (logic 1.220ns (66.369%)  route 0.618ns (33.631%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD + CPR)
    Destination Clock Delay (DCD):    4.846ns = ( 14.846 - 10.000 ) 
    Source Clock Delay      (SCD):    5.142ns
    Clock Pessimism Removal (CPR):    0.296ns
  Clock Uncertainty:      0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.071ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.621     5.142    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[1]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.456     5.598 r  sseg/count_reg[1]/Q
                         net (fo=1, routed)           0.618     6.216    sseg/count_reg_n_0_[1]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[1]_O[3])
                                                      0.764     6.980 r  sseg/count_reg[0]_i_1/O[3]
                         net (fo=1, routed)           0.000     6.980    sseg/count_reg[0]_i_1_n_4
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)       10.000    10.000 r  
    W5                                                0.000    10.000 r  clk (IN)
                         net (fo=0)                   0.000    10.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.388    11.388 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.862    13.250    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.091    13.341 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.505    14.846    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[3]/C
                         clock pessimism              0.296    15.142    
                         clock uncertainty           -0.035    15.107    
    SLICE_X65Y27         FDRE (Setup_fdre_C_D)        0.062    15.169    sseg/count_reg[3]
  -------------------------------------------------------------------
                         required time                         15.169    
                         arrival time                          -6.980    
  -------------------------------------------------------------------
                         slack                                  8.188    





Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) :             0.252ns  (arrival time - required time)
  Source:                 sseg/count_reg[3]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[3]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.357ns  (logic 0.249ns (69.714%)  route 0.108ns (30.286%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.980ns
    Source Clock Delay      (SCD):    1.468ns
    Clock Pessimism Removal (CPR):    0.512ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.585     1.468    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[3]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.141     1.609 r  sseg/count_reg[3]/Q
                         net (fo=1, routed)           0.108     1.717    sseg/count_reg_n_0_[3]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.108     1.825 r  sseg/count_reg[0]_i_1/O[3]
                         net (fo=1, routed)           0.000     1.825    sseg/count_reg[0]_i_1_n_4
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[3]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.853     1.980    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[3]/C
                         clock pessimism             -0.512     1.468    
    SLICE_X65Y27         FDRE (Hold_fdre_C_D)         0.105     1.573    sseg/count_reg[3]
  -------------------------------------------------------------------
                         required time                         -1.573    
                         arrival time                           1.825    
  -------------------------------------------------------------------
                         slack                                  0.252    

Slack (MET) :             0.252ns  (arrival time - required time)
  Source:                 sseg/count_reg[7]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[7]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.357ns  (logic 0.249ns (69.714%)  route 0.108ns (30.286%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.981ns
    Source Clock Delay      (SCD):    1.468ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.585     1.468    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[7]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y28         FDRE (Prop_fdre_C_Q)         0.141     1.609 r  sseg/count_reg[7]/Q
                         net (fo=1, routed)           0.108     1.717    sseg/count_reg_n_0_[7]
    SLICE_X65Y28         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.108     1.825 r  sseg/count_reg[4]_i_1/O[3]
                         net (fo=1, routed)           0.000     1.825    sseg/count_reg[4]_i_1_n_4
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[7]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.854     1.981    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[7]/C
                         clock pessimism             -0.513     1.468    
    SLICE_X65Y28         FDRE (Hold_fdre_C_D)         0.105     1.573    sseg/count_reg[7]
  -------------------------------------------------------------------
                         required time                         -1.573    
                         arrival time                           1.825    
  -------------------------------------------------------------------
                         slack                                  0.252    

Slack (MET) :             0.256ns  (arrival time - required time)
  Source:                 sseg/count_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[4]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.361ns  (logic 0.256ns (70.880%)  route 0.105ns (29.120%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.981ns
    Source Clock Delay      (SCD):    1.468ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.585     1.468    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y28         FDRE (Prop_fdre_C_Q)         0.141     1.609 r  sseg/count_reg[4]/Q
                         net (fo=1, routed)           0.105     1.714    sseg/count_reg_n_0_[4]
    SLICE_X65Y28         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.115     1.829 r  sseg/count_reg[4]_i_1/O[0]
                         net (fo=1, routed)           0.000     1.829    sseg/count_reg[4]_i_1_n_7
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[4]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.854     1.981    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[4]/C
                         clock pessimism             -0.513     1.468    
    SLICE_X65Y28         FDRE (Hold_fdre_C_D)         0.105     1.573    sseg/count_reg[4]
  -------------------------------------------------------------------
                         required time                         -1.573    
                         arrival time                           1.829    
  -------------------------------------------------------------------
                         slack                                  0.256    

Slack (MET) :             0.256ns  (arrival time - required time)
  Source:                 sseg/count_reg[8]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[8]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.361ns  (logic 0.256ns (70.880%)  route 0.105ns (29.120%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.982ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[8]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 r  sseg/count_reg[8]/Q
                         net (fo=1, routed)           0.105     1.715    sseg/count_reg_n_0_[8]
    SLICE_X65Y29         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.115     1.830 r  sseg/count_reg[8]_i_1/O[0]
                         net (fo=1, routed)           0.000     1.830    sseg/count_reg[8]_i_1_n_7
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[8]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.855     1.982    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[8]/C
                         clock pessimism             -0.513     1.469    
    SLICE_X65Y29         FDRE (Hold_fdre_C_D)         0.105     1.574    sseg/count_reg[8]
  -------------------------------------------------------------------
                         required time                         -1.574    
                         arrival time                           1.830    
  -------------------------------------------------------------------
                         slack                                  0.256    

Slack (MET) :             0.256ns  (arrival time - required time)
  Source:                 sseg/count_reg[2]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[2]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.361ns  (logic 0.252ns (69.733%)  route 0.109ns (30.267%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.980ns
    Source Clock Delay      (SCD):    1.468ns
    Clock Pessimism Removal (CPR):    0.512ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.585     1.468    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[2]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y27         FDRE (Prop_fdre_C_Q)         0.141     1.609 r  sseg/count_reg[2]/Q
                         net (fo=1, routed)           0.109     1.719    sseg/count_reg_n_0_[2]
    SLICE_X65Y27         CARRY4 (Prop_carry4_S[2]_O[2])
                                                      0.111     1.830 r  sseg/count_reg[0]_i_1/O[2]
                         net (fo=1, routed)           0.000     1.830    sseg/count_reg[0]_i_1_n_5
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[2]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.853     1.980    sseg/clk
    SLICE_X65Y27         FDRE                                         r  sseg/count_reg[2]/C
                         clock pessimism             -0.512     1.468    
    SLICE_X65Y27         FDRE (Hold_fdre_C_D)         0.105     1.573    sseg/count_reg[2]
  -------------------------------------------------------------------
                         required time                         -1.573    
                         arrival time                           1.830    
  -------------------------------------------------------------------
                         slack                                  0.256    

Slack (MET) :             0.256ns  (arrival time - required time)
  Source:                 sseg/count_reg[6]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[6]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.361ns  (logic 0.252ns (69.733%)  route 0.109ns (30.267%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.981ns
    Source Clock Delay      (SCD):    1.468ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.585     1.468    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[6]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y28         FDRE (Prop_fdre_C_Q)         0.141     1.609 r  sseg/count_reg[6]/Q
                         net (fo=1, routed)           0.109     1.719    sseg/count_reg_n_0_[6]
    SLICE_X65Y28         CARRY4 (Prop_carry4_S[2]_O[2])
                                                      0.111     1.830 r  sseg/count_reg[4]_i_1/O[2]
                         net (fo=1, routed)           0.000     1.830    sseg/count_reg[4]_i_1_n_5
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[6]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.854     1.981    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[6]/C
                         clock pessimism             -0.513     1.468    
    SLICE_X65Y28         FDRE (Hold_fdre_C_D)         0.105     1.573    sseg/count_reg[6]
  -------------------------------------------------------------------
                         required time                         -1.573    
                         arrival time                           1.830    
  -------------------------------------------------------------------
                         slack                                  0.256    

Slack (MET) :             0.264ns  (arrival time - required time)
  Source:                 sseg/count_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[11]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.369ns  (logic 0.249ns (67.412%)  route 0.120ns (32.588%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.982ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 r  sseg/count_reg[11]/Q
                         net (fo=7, routed)           0.120     1.730    sseg/p_0_in[1]
    SLICE_X65Y29         CARRY4 (Prop_carry4_S[3]_O[3])
                                                      0.108     1.838 r  sseg/count_reg[8]_i_1/O[3]
                         net (fo=1, routed)           0.000     1.838    sseg/count_reg[8]_i_1_n_4
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[11]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.855     1.982    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[11]/C
                         clock pessimism             -0.513     1.469    
    SLICE_X65Y29         FDRE (Hold_fdre_C_D)         0.105     1.574    sseg/count_reg[11]
  -------------------------------------------------------------------
                         required time                         -1.574    
                         arrival time                           1.838    
  -------------------------------------------------------------------
                         slack                                  0.264    

Slack (MET) :             0.268ns  (arrival time - required time)
  Source:                 sseg/count_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[12]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.373ns  (logic 0.256ns (68.576%)  route 0.117ns (31.424%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.983ns
    Source Clock Delay      (SCD):    1.470ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.587     1.470    sseg/clk
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y30         FDRE (Prop_fdre_C_Q)         0.141     1.611 r  sseg/count_reg[12]/Q
                         net (fo=7, routed)           0.117     1.728    sseg/p_0_in[2]
    SLICE_X65Y30         CARRY4 (Prop_carry4_S[0]_O[0])
                                                      0.115     1.843 r  sseg/count_reg[12]_i_1/O[0]
                         net (fo=1, routed)           0.000     1.843    sseg/count_reg[12]_i_1_n_7
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.856     1.983    sseg/clk
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/C
                         clock pessimism             -0.513     1.470    
    SLICE_X65Y30         FDRE (Hold_fdre_C_D)         0.105     1.575    sseg/count_reg[12]
  -------------------------------------------------------------------
                         required time                         -1.575    
                         arrival time                           1.843    
  -------------------------------------------------------------------
                         slack                                  0.268    

Slack (MET) :             0.269ns  (arrival time - required time)
  Source:                 sseg/count_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[10]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.374ns  (logic 0.252ns (67.456%)  route 0.122ns (32.544%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.982ns
    Source Clock Delay      (SCD):    1.469ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 r  sseg/count_reg[10]/Q
                         net (fo=9, routed)           0.122     1.732    sseg/p_0_in[0]
    SLICE_X65Y29         CARRY4 (Prop_carry4_S[2]_O[2])
                                                      0.111     1.843 r  sseg/count_reg[8]_i_1/O[2]
                         net (fo=1, routed)           0.000     1.843    sseg/count_reg[8]_i_1_n_5
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.855     1.982    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/C
                         clock pessimism             -0.513     1.469    
    SLICE_X65Y29         FDRE (Hold_fdre_C_D)         0.105     1.574    sseg/count_reg[10]
  -------------------------------------------------------------------
                         required time                         -1.574    
                         arrival time                           1.843    
  -------------------------------------------------------------------
                         slack                                  0.269    

Slack (MET) :             0.292ns  (arrival time - required time)
  Source:                 sseg/count_reg[4]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            sseg/count_reg[5]/D
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Path Group:             clk
  Path Type:              Hold (Min at Fast Process Corner)
  Requirement:            0.000ns  (clk rise@0.000ns - clk rise@0.000ns)
  Data Path Delay:        0.397ns  (logic 0.292ns (73.520%)  route 0.105ns (26.480%))
  Logic Levels:           1  (CARRY4=1)
  Clock Path Skew:        0.000ns (DCD - SCD - CPR)
    Destination Clock Delay (DCD):    1.981ns
    Source Clock Delay      (SCD):    1.468ns
    Clock Pessimism Removal (CPR):    0.513ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.585     1.468    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[4]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y28         FDRE (Prop_fdre_C_Q)         0.141     1.609 r  sseg/count_reg[4]/Q
                         net (fo=1, routed)           0.105     1.714    sseg/count_reg_n_0_[4]
    SLICE_X65Y28         CARRY4 (Prop_carry4_S[0]_O[1])
                                                      0.151     1.865 r  sseg/count_reg[4]_i_1/O[1]
                         net (fo=1, routed)           0.000     1.865    sseg/count_reg[4]_i_1_n_6
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[5]/D
  -------------------------------------------------------------------    -------------------

                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.414     0.414 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.685     1.099    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.029     1.128 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.854     1.981    sseg/clk
    SLICE_X65Y28         FDRE                                         r  sseg/count_reg[5]/C
                         clock pessimism             -0.513     1.468    
    SLICE_X65Y28         FDRE (Hold_fdre_C_D)         0.105     1.573    sseg/count_reg[5]
  -------------------------------------------------------------------
                         required time                         -1.573    
                         arrival time                           1.865    
  -------------------------------------------------------------------
                         slack                                  0.292    





Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name:         clk
Waveform(ns):       { 0.000 5.000 }
Period(ns):         10.000
Sources:            { clk }

Check Type        Corner  Lib Pin  Reference Pin  Required(ns)  Actual(ns)  Slack(ns)  Location       Pin
Min Period        n/a     BUFG/I   n/a            2.155         10.000      7.845      BUFGCTRL_X0Y0  clk_IBUF_BUFG_inst/I
Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X65Y27   sseg/count_reg[0]/C
Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X65Y29   sseg/count_reg[10]/C
Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X65Y29   sseg/count_reg[11]/C
Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X65Y30   sseg/count_reg[12]/C
Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X65Y27   sseg/count_reg[1]/C
Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X65Y27   sseg/count_reg[2]/C
Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X65Y27   sseg/count_reg[3]/C
Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X65Y28   sseg/count_reg[4]/C
Min Period        n/a     FDRE/C   n/a            1.000         10.000      9.000      SLICE_X65Y28   sseg/count_reg[5]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y27   sseg/count_reg[0]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y27   sseg/count_reg[0]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y29   sseg/count_reg[10]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y29   sseg/count_reg[10]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y29   sseg/count_reg[11]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y29   sseg/count_reg[11]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y30   sseg/count_reg[12]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y30   sseg/count_reg[12]/C
Low Pulse Width   Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y27   sseg/count_reg[1]/C
Low Pulse Width   Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y27   sseg/count_reg[1]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y27   sseg/count_reg[0]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y27   sseg/count_reg[0]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y29   sseg/count_reg[10]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y29   sseg/count_reg[10]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y29   sseg/count_reg[11]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y29   sseg/count_reg[11]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y30   sseg/count_reg[12]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y30   sseg/count_reg[12]/C
High Pulse Width  Slow    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y27   sseg/count_reg[1]/C
High Pulse Width  Fast    FDRE/C   n/a            0.500         5.000       4.500      SLICE_X65Y27   sseg/count_reg[1]/C



--------------------------------------------------------------------------------------
Path Group:  (none)
From Clock:  clk
  To Clock:  

Max Delay             9 Endpoints
Min Delay             9 Endpoints
--------------------------------------------------------------------------------------


Max Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 sseg/count_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            seg[4]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        7.355ns  (logic 4.330ns (58.874%)  route 3.025ns (41.126%))
  Logic Levels:           2  (LUT1=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.625     5.146    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.456     5.602 f  sseg/count_reg[10]/Q
                         net (fo=9, routed)           1.351     6.953    sseg/p_0_in[0]
    SLICE_X65Y17         LUT1 (Prop_lut1_I0_O)        0.152     7.105 r  sseg/seg_OBUF[4]_inst_i_1/O
                         net (fo=1, routed)           1.674     8.779    seg_OBUF[4]
    U5                   OBUF (Prop_obuf_I_O)         3.722    12.501 r  seg_OBUF[4]_inst/O
                         net (fo=0)                   0.000    12.501    seg[4]
    U5                                                                r  seg[4] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            seg[6]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        7.353ns  (logic 4.111ns (55.918%)  route 3.241ns (44.082%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.626     5.147    sseg/clk
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y30         FDRE (Prop_fdre_C_Q)         0.456     5.603 r  sseg/count_reg[12]/Q
                         net (fo=7, routed)           0.977     6.580    sseg/p_0_in[2]
    SLICE_X64Y27         LUT3 (Prop_lut3_I2_O)        0.124     6.704 r  sseg/seg_OBUF[6]_inst_i_1/O
                         net (fo=2, routed)           2.264     8.969    seg_OBUF[3]
    U7                   OBUF (Prop_obuf_I_O)         3.531    12.500 r  seg_OBUF[6]_inst/O
                         net (fo=0)                   0.000    12.500    seg[6]
    U7                                                                r  seg[6] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            seg[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        7.189ns  (logic 4.317ns (60.042%)  route 2.873ns (39.958%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.626     5.147    sseg/clk
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y30         FDRE (Prop_fdre_C_Q)         0.456     5.603 r  sseg/count_reg[12]/Q
                         net (fo=7, routed)           0.977     6.580    sseg/p_0_in[2]
    SLICE_X64Y27         LUT3 (Prop_lut3_I2_O)        0.146     6.726 r  sseg/seg_OBUF[0]_inst_i_1/O
                         net (fo=1, routed)           1.896     8.622    seg_OBUF[0]
    W7                   OBUF (Prop_obuf_I_O)         3.715    12.337 r  seg_OBUF[0]_inst/O
                         net (fo=0)                   0.000    12.337    seg[0]
    W7                                                                r  seg[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ssel[3]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        7.125ns  (logic 4.326ns (60.720%)  route 2.799ns (39.280%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.626     5.147    sseg/clk
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y30         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  sseg/count_reg[12]/Q
                         net (fo=7, routed)           0.986     6.589    sseg/p_0_in[2]
    SLICE_X64Y27         LUT3 (Prop_lut3_I1_O)        0.153     6.742 r  sseg/ssel_OBUF[3]_inst_i_1/O
                         net (fo=1, routed)           1.813     8.555    ssel_OBUF[3]
    W4                   OBUF (Prop_obuf_I_O)         3.717    12.272 r  ssel_OBUF[3]_inst/O
                         net (fo=0)                   0.000    12.272    ssel[3]
    W4                                                                r  ssel[3] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            seg[5]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        7.100ns  (logic 4.084ns (57.530%)  route 3.015ns (42.470%))
  Logic Levels:           2  (LUT1=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.625     5.146    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.456     5.602 f  sseg/count_reg[10]/Q
                         net (fo=9, routed)           1.351     6.953    sseg/p_0_in[0]
    SLICE_X65Y17         LUT1 (Prop_lut1_I0_O)        0.124     7.077 r  sseg/seg_OBUF[5]_inst_i_1/O
                         net (fo=1, routed)           1.664     8.741    seg_OBUF[5]
    V5                   OBUF (Prop_obuf_I_O)         3.504    12.246 r  seg_OBUF[5]_inst/O
                         net (fo=0)                   0.000    12.246    seg[5]
    V5                                                                r  seg[5] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            seg[3]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        7.008ns  (logic 4.116ns (58.729%)  route 2.892ns (41.271%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.626     5.147    sseg/clk
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y30         FDRE (Prop_fdre_C_Q)         0.456     5.603 r  sseg/count_reg[12]/Q
                         net (fo=7, routed)           0.977     6.580    sseg/p_0_in[2]
    SLICE_X64Y27         LUT3 (Prop_lut3_I2_O)        0.124     6.704 r  sseg/seg_OBUF[6]_inst_i_1/O
                         net (fo=2, routed)           1.915     8.619    seg_OBUF[3]
    V8                   OBUF (Prop_obuf_I_O)         3.536    12.155 r  seg_OBUF[3]_inst/O
                         net (fo=0)                   0.000    12.155    seg[3]
    V8                                                                r  seg[3] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ssel[1]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        6.967ns  (logic 4.331ns (62.168%)  route 2.636ns (37.832%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.626     5.147    sseg/clk
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y30         FDRE (Prop_fdre_C_Q)         0.456     5.603 r  sseg/count_reg[12]/Q
                         net (fo=7, routed)           0.969     6.572    sseg/p_0_in[2]
    SLICE_X64Y27         LUT3 (Prop_lut3_I2_O)        0.152     6.724 r  sseg/ssel_OBUF[1]_inst_i_1/O
                         net (fo=1, routed)           1.667     8.391    ssel_OBUF[1]
    U4                   OBUF (Prop_obuf_I_O)         3.723    12.114 r  ssel_OBUF[1]_inst/O
                         net (fo=0)                   0.000    12.114    ssel[1]
    U4                                                                r  ssel[1] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ssel[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        6.917ns  (logic 4.083ns (59.027%)  route 2.834ns (40.973%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.626     5.147    sseg/clk
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y30         FDRE (Prop_fdre_C_Q)         0.456     5.603 r  sseg/count_reg[12]/Q
                         net (fo=7, routed)           0.969     6.572    sseg/p_0_in[2]
    SLICE_X64Y27         LUT3 (Prop_lut3_I2_O)        0.124     6.696 r  sseg/ssel_OBUF[0]_inst_i_1/O
                         net (fo=1, routed)           1.865     8.561    ssel_OBUF[0]
    U2                   OBUF (Prop_obuf_I_O)         3.503    12.064 r  ssel_OBUF[0]_inst/O
                         net (fo=0)                   0.000    12.064    ssel[0]
    U2                                                                r  ssel[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[12]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ssel[2]
                            (output port)
  Path Group:             (none)
  Path Type:              Max at Slow Process Corner
  Data Path Delay:        6.749ns  (logic 4.103ns (60.795%)  route 2.646ns (39.205%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         1.458     1.458 r  clk_IBUF_inst/O
                         net (fo=1, routed)           1.967     3.425    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.096     3.521 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          1.626     5.147    sseg/clk
    SLICE_X65Y30         FDRE                                         r  sseg/count_reg[12]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y30         FDRE (Prop_fdre_C_Q)         0.456     5.603 f  sseg/count_reg[12]/Q
                         net (fo=7, routed)           0.986     6.589    sseg/p_0_in[2]
    SLICE_X64Y27         LUT3 (Prop_lut3_I0_O)        0.124     6.713 r  sseg/ssel_OBUF[2]_inst_i_1/O
                         net (fo=1, routed)           1.660     8.373    ssel_OBUF[2]
    V4                   OBUF (Prop_obuf_I_O)         3.523    11.896 r  ssel_OBUF[2]_inst/O
                         net (fo=0)                   0.000    11.896    ssel[2]
    V4                                                                r  ssel[2] (OUT)
  -------------------------------------------------------------------    -------------------





Min Delay Paths
--------------------------------------------------------------------------------------
Slack:                    inf
  Source:                 sseg/count_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ssel[2]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        1.920ns  (logic 1.410ns (73.435%)  route 0.510ns (26.565%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 r  sseg/count_reg[11]/Q
                         net (fo=7, routed)           0.179     1.789    sseg/p_0_in[1]
    SLICE_X64Y27         LUT3 (Prop_lut3_I2_O)        0.045     1.834 r  sseg/ssel_OBUF[2]_inst_i_1/O
                         net (fo=1, routed)           0.331     2.165    ssel_OBUF[2]
    V4                   OBUF (Prop_obuf_I_O)         1.224     3.389 r  ssel_OBUF[2]_inst/O
                         net (fo=0)                   0.000     3.389    ssel[2]
    V4                                                                r  ssel[2] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ssel[3]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.044ns  (logic 1.469ns (71.878%)  route 0.575ns (28.122%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 f  sseg/count_reg[11]/Q
                         net (fo=7, routed)           0.179     1.789    sseg/p_0_in[1]
    SLICE_X64Y27         LUT3 (Prop_lut3_I2_O)        0.049     1.838 r  sseg/ssel_OBUF[3]_inst_i_1/O
                         net (fo=1, routed)           0.396     2.234    ssel_OBUF[3]
    W4                   OBUF (Prop_obuf_I_O)         1.279     3.513 r  ssel_OBUF[3]_inst/O
                         net (fo=0)                   0.000     3.513    ssel[3]
    W4                                                                r  ssel[3] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ssel[1]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.108ns  (logic 1.459ns (69.224%)  route 0.649ns (30.776%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 f  sseg/count_reg[11]/Q
                         net (fo=7, routed)           0.314     1.924    sseg/p_0_in[1]
    SLICE_X64Y27         LUT3 (Prop_lut3_I0_O)        0.045     1.969 r  sseg/ssel_OBUF[1]_inst_i_1/O
                         net (fo=1, routed)           0.335     2.304    ssel_OBUF[1]
    U4                   OBUF (Prop_obuf_I_O)         1.273     3.577 r  ssel_OBUF[1]_inst/O
                         net (fo=0)                   0.000     3.577    ssel[1]
    U4                                                                r  ssel[1] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[11]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            ssel[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.108ns  (logic 1.390ns (65.932%)  route 0.718ns (34.068%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[11]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 r  sseg/count_reg[11]/Q
                         net (fo=7, routed)           0.314     1.924    sseg/p_0_in[1]
    SLICE_X64Y27         LUT3 (Prop_lut3_I0_O)        0.045     1.969 r  sseg/ssel_OBUF[0]_inst_i_1/O
                         net (fo=1, routed)           0.404     2.373    ssel_OBUF[0]
    U2                   OBUF (Prop_obuf_I_O)         1.204     3.577 r  ssel_OBUF[0]_inst/O
                         net (fo=0)                   0.000     3.577    ssel[0]
    U2                                                                r  ssel[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            seg[3]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.187ns  (logic 1.422ns (65.033%)  route 0.765ns (34.967%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 f  sseg/count_reg[10]/Q
                         net (fo=9, routed)           0.301     1.912    sseg/p_0_in[0]
    SLICE_X64Y27         LUT3 (Prop_lut3_I0_O)        0.045     1.957 r  sseg/seg_OBUF[6]_inst_i_1/O
                         net (fo=2, routed)           0.463     2.420    seg_OBUF[3]
    V8                   OBUF (Prop_obuf_I_O)         1.236     3.656 r  seg_OBUF[3]_inst/O
                         net (fo=0)                   0.000     3.656    seg[3]
    V8                                                                r  seg[3] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            seg[0]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.217ns  (logic 1.465ns (66.068%)  route 0.752ns (33.932%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 f  sseg/count_reg[10]/Q
                         net (fo=9, routed)           0.301     1.912    sseg/p_0_in[0]
    SLICE_X64Y27         LUT3 (Prop_lut3_I0_O)        0.046     1.958 r  sseg/seg_OBUF[0]_inst_i_1/O
                         net (fo=1, routed)           0.451     2.408    seg_OBUF[0]
    W7                   OBUF (Prop_obuf_I_O)         1.278     3.686 r  seg_OBUF[0]_inst/O
                         net (fo=0)                   0.000     3.686    seg[0]
    W7                                                                r  seg[0] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            seg[5]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.266ns  (logic 1.392ns (61.417%)  route 0.874ns (38.583%))
  Logic Levels:           2  (LUT1=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 f  sseg/count_reg[10]/Q
                         net (fo=9, routed)           0.543     2.153    sseg/p_0_in[0]
    SLICE_X65Y17         LUT1 (Prop_lut1_I0_O)        0.045     2.198 r  sseg/seg_OBUF[5]_inst_i_1/O
                         net (fo=1, routed)           0.331     2.529    seg_OBUF[5]
    V5                   OBUF (Prop_obuf_I_O)         1.206     3.735 r  seg_OBUF[5]_inst/O
                         net (fo=0)                   0.000     3.735    seg[5]
    V5                                                                r  seg[5] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            seg[6]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.331ns  (logic 1.418ns (60.842%)  route 0.913ns (39.158%))
  Logic Levels:           2  (LUT3=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 f  sseg/count_reg[10]/Q
                         net (fo=9, routed)           0.301     1.912    sseg/p_0_in[0]
    SLICE_X64Y27         LUT3 (Prop_lut3_I0_O)        0.045     1.957 r  sseg/seg_OBUF[6]_inst_i_1/O
                         net (fo=2, routed)           0.611     2.568    seg_OBUF[3]
    U7                   OBUF (Prop_obuf_I_O)         1.232     3.800 r  seg_OBUF[6]_inst/O
                         net (fo=0)                   0.000     3.800    seg[6]
    U7                                                                r  seg[6] (OUT)
  -------------------------------------------------------------------    -------------------

Slack:                    inf
  Source:                 sseg/count_reg[10]/C
                            (rising edge-triggered cell FDRE clocked by clk  {rise@0.000ns fall@5.000ns period=10.000ns})
  Destination:            seg[4]
                            (output port)
  Path Group:             (none)
  Path Type:              Min at Fast Process Corner
  Data Path Delay:        2.339ns  (logic 1.468ns (62.770%)  route 0.871ns (37.230%))
  Logic Levels:           2  (LUT1=1 OBUF=1)
  Clock Uncertainty:      0.025ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter     (TSJ):    0.050ns
    Total Input Jitter      (TIJ):    0.000ns
    Discrete Jitter          (DJ):    0.000ns
    Phase Error              (PE):    0.000ns

    Location             Delay type                Incr(ns)  Path(ns)    Netlist Resource(s)
  -------------------------------------------------------------------    -------------------
                         (clock clk rise edge)        0.000     0.000 r  
    W5                                                0.000     0.000 r  clk (IN)
                         net (fo=0)                   0.000     0.000    clk
    W5                   IBUF (Prop_ibuf_I_O)         0.226     0.226 r  clk_IBUF_inst/O
                         net (fo=1, routed)           0.631     0.858    clk_IBUF
    BUFGCTRL_X0Y0        BUFG (Prop_bufg_I_O)         0.026     0.884 r  clk_IBUF_BUFG_inst/O
                         net (fo=13, routed)          0.586     1.469    sseg/clk
    SLICE_X65Y29         FDRE                                         r  sseg/count_reg[10]/C
  -------------------------------------------------------------------    -------------------
    SLICE_X65Y29         FDRE (Prop_fdre_C_Q)         0.141     1.610 f  sseg/count_reg[10]/Q
                         net (fo=9, routed)           0.543     2.153    sseg/p_0_in[0]
    SLICE_X65Y17         LUT1 (Prop_lut1_I0_O)        0.044     2.197 r  sseg/seg_OBUF[4]_inst_i_1/O
                         net (fo=1, routed)           0.328     2.525    seg_OBUF[4]
    U5                   OBUF (Prop_obuf_I_O)         1.283     3.808 r  seg_OBUF[4]_inst/O
                         net (fo=0)                   0.000     3.808    seg[4]
    U5                                                                r  seg[4] (OUT)
  -------------------------------------------------------------------    -------------------





